Principal ASIC RTL Design Engineer

Comprehensive Professional Solutions, Inc.

Our client is seeking a Principal ASIC RTL Design Engineer to join their Irvine, CA design center team.

Our client is seeking a Principal ASIC RTL Design Engineer to join their Irvine, CA design center team. In this role, you will focus on the following:
 
Principal ASIC RTL Design Engineer
  • Work with architects and leads to understand features to be implemented and verified
  • Micro Architecture and Design documentation creation
  • Design capture using Verilog / System Verilog to optimize performance, area and power
  • Initial verification and debugging test failures
  • Specify cover points, reviewing functional and code coverage results and assisting to increase coverage
  • Provide assistance to resolve synthesis and timing analysis issues
Required Skills
  • Experience in RTL level ASIC design, including use of a source control system and experience debugging RTL code using simulation tools
  • Prototype lab bring up and silicon validation experience for at least one device
  • Datapath / Packet processing experience 
  • PCIE Gen4 / 5 protocol understanding and experience
  • Expert in Verilog, System Verilog and proficient in verification, timing analysis and optimization
  • Experience working in Linux and Windows environments
  • Familiarity with Synthesis, STA and Design Audit tools like Spyglass
  • Solid knowledge of computer architecture and circuit issues/analysis is a bonus, though a basic working knowledge of these areas is essential
  • Strong analytical thinking and problem-solving skills, excellent attention to detail, and good coding skills and style required
  • UVM familiarity is desirable
  • Low power design techniques and tool scripting (e.g. Perl) is a plus
  • Compression / decompression and encryption / decryption experience is a plus
  • Ability to work with a team to achieve individual and joint goals
  • Ability to communicate effectively verbally and in writing
  • MS in Electrical or Computer Engineering and 6 years or experience or Ph.D. and 3 years of experience